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IBM unveils new Silicon Nanophotonic chip technology; furthering Exascale computing efforts

CMOS silicon nanophotonics
IBM has unveiled a new chip technology, called CMOS Integrated Silicon Nanophotonics chip technology, which enables a 10X improvement in integration density and produces smaller, faster and more power-efficient chips than is possible with conventional technologies. Click to enlarge.

IBM scientists unveiled a new chip technology—CMOS Integrated Silicon Nanophotonics—that integrates electrical and optical devices on the same piece of silicon, enabling computer chips to communicate using pulses of light (instead of electrical signals), resulting in smaller, faster and more power-efficient chips than is possible with conventional technologies.

IBM anticipates that Silicon Nanophotonics will dramatically increase the speed and performance between chips, and further the company’s Exascale computing program, which is aimed at developing a supercomputer that can perform one million trillion calculations—an Exaflop—in a single second. An Exascale supercomputer will be approximately one thousand times faster than the fastest machine today. Exascale computing is of high interest to the Department of Energy for application in numerous areas including advanced combustion modeling and battery development. (Earlier post.)

The new technology is the result of a decade of development at IBM’s global Research laboratories. The patented technology will change and improve the way computer chips communicate by integrating optical devices and functions directly onto a silicon chip, enabling a more than 10X improvement in integration density than is feasible with current manufacturing techniques.

The development of the Silicon Nanophotonics technology brings the vision of on-chip optical interconnections much closer to reality. With optical communications embedded into the processor chips, the prospect of building power-efficient computer systems with performance at the Exaflop level is one step closer to reality.

—Dr. T.C. Chen, vice president, Science and Technology, IBM Research

In addition to combining electrical and optical devices on a single chip, the new IBM technology can be produced on the front-end of a standard CMOS manufacturing line and requires no new or special tooling. With this approach, silicon transistors can share the same silicon layer with silicon nanophotonics devices. To make this approach possible, IBM researchers have developed a suite of integrated ultra-compact active and passive silicon nanophotonics devices that are all scaled down to the diffraction limit—the smallest size that dielectric optics can afford.

Our CMOS Integrated Nanophotonics breakthrough promises unprecedented increases in silicon chip function and performance via ubiquitous low-power optical communications between racks, modules, chips or even within a single chip itself. The next step in this advancement is to establishing manufacturability of this process in a commercial foundry using IBM deeply scaled CMOS processes.

—Dr. Yurii A. Vlasov, Manager of the Silicon Nanophotonics Department at IBM Research

By adding just a few more processing modules to a standard CMOS fabrication flow, the technology enables a variety of silicon nanophotonics components, such as: modulators, germanium photodetectors and ultra-compact wavelength-division multiplexers to be integrated with high-performance analog and digital CMOS circuitry. As a result, single-chip optical communications transceivers can now be manufactured in a standard CMOS foundry, rather than assembled from multiple parts made with expensive compound semiconductor technology.

The density of optical and electrical integration demonstrated by IBM’s new technology is unprecedented, the company says: a single transceiver channel with all accompanying optical and electrical circuitry occupies only 0.5 mm2—10 times smaller than previously announced by others. The technology is amenable for building single-chip transceivers with area as small as 4x4 mm2 that can receive and transmit more than Terabits per second—i.e., more than a trillion bits per second.

The development of CMOS Integrated Silicon Nanophotonics is the culmination of a series of related advancements by IBM Research that resulted in the development of deeply scaled front-end integrated Nanophotonics components for optical communications. These milestones include:

  • March 2010, IBM announced a Germanium Avalanche Photodetector working at unprecedented 40Gb/s with CMOS compatible voltages as low as 1.5V. This was the last piece of the puzzle that completes the prior development of the “nanophotonics toolbox” of devices necessary to build the on-chip interconnects.

  • March 2008, IBM scientists announced the world’s tiniest nanophotonic switch for “directing traffic” in on-chip optical communications, ensuring that optical messages can be efficiently routed.

  • December 2007, IBM scientists announced the development of an ultra-compact silicon electro-optic modulator, which converts electrical signals into the light pulses, a prerequisite for enabling on-chip optical communications.

  • December 2006, IBM scientists demonstrated silicon nanophotonic delay line that was used to buffer over a byte of information encoded in optical pulses—a requirement for building optical buffers for on-chip optical communications.

Dr. Vlasov reported details and results of this research effort today in a talk at the major international semiconductor industry conference SEMICON being held in Tokyo. The talk is entitled “CMOS Integrated Silicon Nanophotonics: Enabling Technology for Exascale Computational Systems” co-authored by William Green, Solomon Assefa, Alexander Rylyakov, Clint Schow, Folkert Horst, and Yurii Vlasov of IBM’s T.J. Watson Research Center in Yorktown Heights, N.Y. and IBM Zurich Research Lab in Rueschlikon, Switzerland.



This is really interesting. Hopefully faster computing will eventually translate someway/somehow into better wireless internet & wi-fi...making cable TV & Satelitte TV providers obsolete.


When will the chipset be available for computer manufacturing?


If EV battery technologies evolution could match half that of chips, we would have had batteries with 10x and 20x the energy density long time ago.

CMOS technologies are also doing a lot to improve photography performance at a lower cost. Very high speed picture rate is now available at lower cost. Surveillance cameras using CMOS sensors will replace others soon due to their inherent capability to capture more high definition details to better identify intruders.


There is much more than a decade of research behind this. IBM has demonstrated the best research practices here: not expecting immediate payoff but rather patiently working away and sticking with it. May they reap huge rewards for this.


Wire based signalling is the major power consumtion source in the chips now. Optical signalling should change this and bring down the power consumption by good amount.

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