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Renesas unveils Gen 3 R-Car system-on-chip for connected and autonomous cars

Japan-based Renesas Electronics Corporation unveiled the third-generation R-Car, an automotive computing platform solution for driving safety support systems and in-vehicle infotainment systems. The new R-Car H3 System-on-Chip (SoC), the first member of the third-generation R-Car, delivers CPU performance; image recognition processing; ISO 26262 (ASIL-B) compliance; and a system in package (SiP) with external memory to enable a wide range of automotive applications.

The R-Car H3 realizes powerful automotive computing performance exceeding that of the predecessor R-Car H2. This enables system manufacturers to utilize the new R-Car H3 as an automotive computing platform to play a key role in the autonomous-driving era.

To make the new device suited for driving safety support systems, the R-Car H3 provides cognitive computing capabilities; an enhanced computing performance that can process large volumes of information from vehicle sensors accurately in real-time; and enables system manufacturers to run applications that require complex processing, such as obstacle detection, driver status recognition, hazard prediction, and hazard avoidance.

To further accelerate the driving safety support systems, the R-Car H3 also conforms to the ISO 26262 (ASIL-B) functionality safety for automotive.

Furthermore, in in-vehicle infotainment systems, the need for connectivity between various systems and services such as smartphones and cloud services is growing. These have led to a significant increase in the volume of data transmitted from outside the system. Therefore, there is a demand for human-machine interface (HMI) computing to process these large amounts of data accurately in real-time. The performance power of the R-Car H3 enables excellent graphics design to realize advanced applications and rich HMI.

Key features of the new R-Car H3:

  1. Support for a wide range of applications as an automotive computing platform. To enable system manufacturers to utilize the R-Car H3 as an automotive computing platform, the new device realizes powerful automotive computing performance exceeding that of the predecessor R-Car H2. To process large amounts of information accurately in real-time, the R-Car H3 is built around the ARM Cortex-A57/A53 cores, employing the newest 64-bit CPU core architecture from ARM. It achieves processing performance of 40,000 DMIPS (Dhrystone million instructions per second) for enhanced processing power.

    The R-Car H3 also features the PowerVR GX6650 as the 3-D graphics engine to deliver reliable information to drivers at the right timing. Based on the latest architecture from Imagination Technologies, it delivers approximately three times the shader calculation () processing performance of the R-Car H2.

    The on-chip IMP-X5 parallel programmable engine offers advanced image recognition technology in addition to the CPU and GPU. Exclusive to Renesas, the IMP-X5 is a recognition engine that is optimized for interoperation with the CPU. It delivers four times the recognition performance of the earlier IMP-X4 image recognition engine, embedded in the second-generation R-Car family.

    The R-Car H3 is the first automotive SoC to adopt the 16nm process. By realizing this high performance as well as compliance with the ISO26262 (ASIL-B) standard for automotive functional safety, the R-Car H3 can be used as an automotive computing platform that supports a wide range of applications, including advanced driving safety support systems and in-vehicle infotainment systems.

  2. Improved system level performance based on the results of rich in-vehicle infotainment systems. Especially by optimizing the internal bus architecture of the SoC, and improving the bandwidth of the DDR memory, the R-Car H3 realizes four times the memory bandwidth compared to the R-Car H2, which enables the system manufacturer to run multiple applications.

    Addressing the demand for higher resolution video playback on multiple displays, the R-Car H3 incorporates video codec engine exclusive to Renesas that supports new video compression formats and achieves two times the video playback performance of the R-Car H2.

    The R-Car H3 also incorporates enhanced security functions for a more robust boot protection process as well as protection against external cyber-attacks.

  3. Availability of SiP modules with external memory to reduce the design workload. SiP modules support high-speed external DDR memory interface design with the R-Car H3. As the connection speed between the SoC and DDR memory rises, and the number of signal lines increases, burdens and complexities of PCB design increase. These have become important issues for system manufacturers.

    By developing modules with an SoC connected to DDR memory, Renesas is reducing the burden as well as the PCB costs and complexities associated with the design. In addition to the SoC and DDR memory, the modules include serial flash memory required for initial boot-up. This means the design tasks from boot-up through DDR memory operation can be eliminated and system manufacturers adopting the R-Car H3 can reduce their design tasks and risks.

The new R-Car H3 maintains a high level of software compatibility with the other SoCs in the R-Car Family already available: the R-Car H2, R-Car M2, and R-Car E2. The R-Car H3 will maintain high level software scalability for the third-generation R-Car Family.

Samples of the R-Car H3 are available now. Mass production is scheduled to begin in March 2018 and is expected to reach a volume of 100,000 units per month in March 2019. (Availability is subject to change without notice.)

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