Toshiba, Japan Semiconductor develop analog power IC process technology enhancing reliability of LDMOS for automotive
Toshiba Electronic Devices & Storage Corporation and its manufacturing subsidiary, Japan Semiconductor Corporation have developed process technology for N-channel Lateral Double Diffused MOS (LDMOS) for 0.13-micron generation analog power ICs that ensures high reliability, even at the high temperatures of automotive applications.
The technology cuts leak current from crystal defects, and boosts the lifetime of LDMOS in high temperature environments (175°C) to ten times that of Toshiba’s current technology.
Details were reported on 22 May at the IEEE-sponsored International Symposium on Power Semiconductor Devices and ICs 2019 (ISPSD 2019) in Shanghai.
Demand on automotive semiconductors is increasing with the electrification of vehicles. Devices used must be able to maintain high level reliability over the long term in a high temperature environment, which is driving interest in N-channel LDMOS, now mainly used in motor control ICs for industrial equipment and consumer electronics.
In LDMOS manufacturing, high-dose ion implantation degrades the crystalline structure of the silicon layer. Higher doses result in more degradation, and increase the undesirable impact on performance characteristics. This results in two significant problems for LDMOS: the larger the area, the more the initial leak current failure; and long-term use in hot environments, such as automotive applications, causes high temperature reverse bias (HTRB) degradation, and drastic increases in leak current.
Toshiba and Japan Semiconductor Corporation found solutions by combining Toshiba’s know-how in transistor design with Japan Semiconductor’s process technologies.
Initial leak current failure due to crystal defects during the manufacturing process was solved by changing the STI (shallow trench isolation) filling material used for LDMOS. Currently, HDP-CVD (High Density Plasma assisted Chemical Vapor Deposition) is used to fill STI on the edge of LDMOS, but replacing it with SA-CVD (Sub-atmospheric Pressure Chemical Vapor Deposition) imposes less stress on the silicon.
With SA-CVD, no chip failure due to leak current was found, because there was no damage to the silicon’s crystalline structure, even during high-dose ion implantation. This confirmed the ability of the new technology to suppress initial leak current failure.
The companies identified the cause of HTRB degradation by analyzing its mechanism, and found that the edge design of LDMOS is key; high-dose implantation near the STI/Si edge resulted in crystal defects in the silicon. While the annealing process, the dangling bond of the silicon is connected by proton that temporarily hides them, the protons de-connected from the dangling bond during HTRB stress, and current leakage due to crystal defects increases.
The companies changed the LDMOS layout to keep the high-dose implanted area away from the highly stressed area close to the STI, and covered the STI/Si interface with gate poly silicon which is used for the gate electrodes in LDMOS. This suppresses the value of the critical stress of the area near the STI, where the high stress exists, and reduces HTRB degradation.
The companies will start mass production of analog ICs for automotive application with the new process technology from July this year.
Toshiba has wide range of lineup of LDMOS for various voltages and applications, and also develops fourth generation LDMOS to decrease on‐resistance half compares to Toshiba’s current devices.