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Arbe Robotics releases production radar processor

Israel-based Arbe Robotics Ltd. has released the production version of its radar processor, which is used for OEM development projects and B-Sample radars with the production functionality of Arbe Tier-1s. Arbe’s radar processor complements the company’s production chipset portfolio which already includes production RF chips.

Arbe’s patented processor chip integrates radar processing unit (RPU) architecture with embedded radar signal processing algorithms to convert massive amounts of raw data while maintaining low silicon power consumption. The automotive-grade system-on-chip (SOC) includes safety processor, security, dual-core DSP, and application processor.

Arbe says that its radar processor is the strongest solution on the market for automotive radars. With its computational abilities, it enables the real-time processing of massive amounts of raw data generated by Arbe’s 2,304 virtual radar channel array (48 receive * 48 transmit) in 30 frames per second. Arbe’s chip demonstrates an improvement of 10X in processing power compared to the current strongest radar processor alternatives.

Arbe’s radar processor can handle raw data input in a max rate of 28.8 Gbps, which is pre-processed in the processor. The internal processing is equal to the rate of 3Tbps while the processor’s output reach point-cloud is provided at a rate of up to 1Gbps. This massive amount of data required building a dedicated processor optimized for radar processing while maintaining low power consumption and offering the lowest price per channel, according to the company.

Arbe’s processor offers advanced hardware acceleration to offload and optimize the massive radar calculations. With the launch of the new processor, Arbe supports 4 times better range resolution with up to 2K range bins, in comparison to the most advanced solution on the market, one mode configuration for short, mid, and long ranges, and scalability to support both surround imaging radars as well as long range front perception radars.

The processor is designed to support software-defined architecture that enables control over radar parameters such as modulation, pre-processing flow, and post processing. A dual core application processor and a dual core DSP with vector unit of 512 bits are available to implement Tier 1 and OEM algorithms.

The processor includes a built-in hardware security module, with encryption accelerators, and key management in a secured island. Additionally, the processor provides AI perception capabilities for hardware that can run perception algorithms on the radar, which includes tracker, preparation for sensor fusion, and free space mapping.


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